1. Field of the Invention
The present invention relates, in general, to semiconductor packaging, and more particularly, to a printed circuit board for use in a ball grid array semiconductor package that prevents the accumulation of an electrostatic charge in the package during molding, thereby preventing damage to the components in the package caused by a rapid discharge of such an electrostatic charge.
2. Description of the Related Art
The recent trend in consumer electronics has been toward smaller, lighter products having improved capabilities and capacities, which has, in turn, resulted in a demand for semiconductor chips that are smaller, more highly integrated, and of higher capacity. Accordingly, modem semiconductor packages must have excellent electrical characteristics, high heat dissipating capabilities, and a large input/output-terminal capacity, to enable such small, highly integrated, and efficient semiconductor chips to perform as expected.
Ball grid array (BGA) semiconductor packages have been proposed and widely used as an exemplary package capable of enabling small, efficient and highly integrated semiconductor chips to meet their design goals effectively. Such BGA packages are easily formed on a conventional printed circuit board (PCB) and can effectively reduce the overall length of electric circuits incorporating them. BGA packages also utilize power- and/or ground-bonding areas more effectively, thus yielding excellent electric characteristics. Also, the input/output terminal density of BGA packages is greater than that of conventional quad flat packages (QFPs), which better comports with the trend toward smaller, denser packages.
FIGS. 8a and 8b are top and bottom plan views, respectively, of a conventional, strip-type multiple-package PCB 10 typically used in the manufacture of BGA semiconductor packages. FIG. 9 is a sectional view of a typical BGA semiconductor package incorporating such a conventional PCB.
As shown in the drawings, the typical PCB 10' comprises a dielectric substrate 11, typically made of a thermosetting resin, e.g., a bismaleimidetriazine or polyimide resin. A plurality of conductive traces 12 are formed on each side of the substrate to form predetermined circuit patterns on each side of the board. A plurality of die, or chip mounting plates 16 are centrally provided on the top surface of the substrate 11 for the mounting of semiconductor chips thereon. A plurality of conductive via holes 13 are formed through the substrate 11 to electrically connect the conductive traces 12 of both sides of the PCB with each other. A plurality of solder ball lands 14 are electrically connected to the conductive traces 12 on the bottom surface of the substrate.
As shown in FIG. 8a, a mold runner gate 17, comprising a thin, conductive metal plate or plating of, e.g., gold or palladium, extends from a corner of the substrate 11 to the chip mounting plate 16, and serves to guide molten molding compound, e.g., a resin, into the region of the chip mounting plate 16 during a package molding operation described in more detail below.
A non-conductive solder mask 15 coats both sides of the substrate 11 outside of selected areas of the conductive traces 12, e.g., around the edge of the chip mounting plate 16, and on the solder ball lands 14, and serves to electrically isolate the traces 12 from each other and to protect them from harmful environmental elements.
The mold runner gate 17 is electrically connected on the PCB 10' to a ground ring 25 formed about the periphery of the chip mounting plate 16 by means of a conductive ground trace 22. The grounded elements of a semiconductor chip (not shown in FIG. 8a), typically ground pads, are electrically connected to the ground ring 25 by means of bonding wires 50 (see FIG. 9) that extend between the chip and the ground ring. In the BGA package, ground signals are applied from the semiconductor chip to the mold runner gate 17, and the voltage drops occurring between the chip and ground can be easily and precisely measured. Likewise, any voltage drops occurring in the wire bonds between the chip and the conductive traces 12 can also be checked easily and precisely. The grounded mold runner gate/grounding ring arrangement therefore forms an effective common ground area for purposes of complete circuit definition within the BGA package.
As seen in FIGS. 8a and 8b, tooling holes 18 are used in the strip-shaped PCB 10 to position and fix the PCB in a package molding tool assembly. Singularizing holes 19 are used as reference points during singularization, or separation, of the individual BGA packages from the multiple-package PCB 10', which is typically accomplished by die cutting. The dotted square 19' defined by the singularizing holes 19 corresponds to the line along which the PCB is cut when the individual BGA packages are separated from the plurality of simultaneously fabricated packages on the PCB 10'.
FIG. 10 is a sectional view through the region around a via hole 13 of the PCB 10'. As shown in the drawing, the via holes 13 are formed between conductive traces 12 on opposite sides of the board to interconnect them through the board. The interior wall of the via hole 13 is plated with a conductive metal, while the solder mask 15 overlays the top surface of the trace 12 and fills the void in the via hole 13. A solder ball 80 is welded to the solder ball land 14 through an opening in the solder mask 15 and is used as an input/output terminal of the BGA package.
FIG. 11 is a sectional view through a tooling hole 18, as taken along the line E'--E' in FIG. 8b. FIG. 12 reveals that the tooling hole 18 is, like the via hole 13, formed through the thickness of the substrate 11 of the PCB. However, unlike the via hole 13, the tooling hole 18 does not include a conductive layer on its interior surface that electrically connects the upper and lower surfaces of the board, nor does the solder mask 15 fill the interior void of the hole.
A conventional BGA semiconductor package 1 that incorporates a conventional PCB 10' of the type described above is shown in elevational cross-section in FIG. 9. Typically, a plurality of such packages are simultaneously fabricated on the PCB 10' in the following manner: First, a plurality of semiconductor chips 40 are mounted, typically by means of a bonding layer (not shown), on the strip-shaped PCB 10', one on each of the chip mounting plates 16. Each chip 40 is then electrically connected to wire bonding areas on the conductive traces 12 (which are free of any solder masking 15) using a plurality of fine, conductive bonding wires 50.
After wire bonding is complete, a plurality of resin envelopes 70 are molded onto the upper surface of the PCB 10 around each of the chips 40 and its associated bonding wires 50 to individually encapsulate and protect them against damaging mechanical and electrical elements in their environment. After molding, a plurality of solder balls 80, which function as the input and/or output terminals of the packages 1, are respectively welded to the solder ball lands 14. The solder ball welding step is followed by a singularizing step in which the simultaneously formed plurality of BGA packages 1 of a reduced, uniform size, are separated from the PCB 10', typically by die cutting, into individual BGA packages 1 of the type illustrated in FIG. 9.
In the above manufacturing process, the molding procedure is carried out with the individual semiconductor chips 40 mounted on the PCB 10' and with the PCB clamped between top and bottom molds 30a and 30b, as shown in FIG. 12. The encapsulating resin reinforces the delicate wires 50 and bonds them securely to both the associated chip 40, the conductive traces 12, and the upper surface of the PCB' 10 in a sealed, monolithic block.
As seen in FIG. 12, the bottom mold 30b has a rectangular depression 31 in its top surface, which serves to seat the PCB 10' therein, while the top mold 30a is provided with a plurality of depressions 31' in its lower surface, each defining a cavity 34 over the PCB 10' having a configuration corresponding to the upper surface of the molded resin envelope 70 of each BGA package 1. A plurality of cavities 34 (FIG. 14) is thus defined by the lower depressions 31' of the top mold 30a and the top surface of the PCB 10, each of which encloses one of the semiconductor chips 40 and its associated bonding wires 50 positioned on the top surface of the PCB 10'.
As seen in the bottom perspective view of the top mold 30a in FIG. 5, a runner 32 is formed in the top mold 30a at a position near the corner of each cavity 34 to guide injected molten molding resin (not shown) into the cavity 34. The runners 32 are formed at positions corresponding to the positions of the respective mold runner gates 17 (see FIG. 8a) on the PCB 10'. The lower surface of the top mold 30a mates with the upper surface of the bottom mold 30b on opposite sides of the PCB 10' such that the runners 32 provide conduits between the top mold 34a and the PCB 10' for the introduction of the resin into the cavities 34.
The molding resin is injected under pressure into the cavity 34 through the runner 32, thereby forming a resin envelope 70 on the upper surface of the PCB 10 that completely encapsulates the chip 40 and its associated bonding wires 50.
The top mold 30a is provided with a plurality of tooling pins 33 that extend through the tooling holes 18 of the PCB 10' and into corresponding apertures (not shown) in the bottom mold 30b, thus locating and securely fixing the PCB 10' between the two molds during the molding process.
Importantly, it will be noted that, when the conventional PCB 10' is clamped between the top and bottom molds 30a, 30b during the molding procedure, all of the conductive surfaces on the PCB 10', e.g., the circuit traces 12 and the solder ball lands 14, are separated from the top and bottom molds 30a, 30b, respectively, by the thickness of the dielectric solder mask 15, i.e., the PCB is electrically isolated from both the top and bottom molds 30a, 30b, respectively, during the molding process.
During molding, hot molten molding resin under high pressure is injected into the cavity 34 through the conduit formed between the runner 32 in the top mold 30a and the mold runner gate 17 on the PCB 10, causing the molten resin to flow past the chip 40, the conductive bonding wires 50, and the surface of the PCB 10' with frictional contact. This frictional flow of the hot resin over these components generates static electricity, which is induced onto the chip 40, the wires 50 and the traces 12 of the PCB 10', thereby causing an undesirable accumulation of a strong electrostatic charge on these elements.
In those cases where the supply voltage specified for the semiconductor chips, or the allowable variation thereof, is relatively high, a rapid discharge of such an accumulated electrostatic charge will not necessarily cause any damage to the components of the BGA package. However, when the level of supply voltage specified for the semiconductor chips or allowable variation thereof is relatively low, then a rapid discharge of such an accumulated charge can cause permanent damage to the semiconductor chip 40, the bonding wires 50 and/or the conductive traces 12 of the BGA packages.
This undesirable discharge can occur when the packages 1 are removed from the molds after the molding process, or when they are brought into contact with other processing equipment during manufacture. When this discharge occurs, the electrical components of the semiconductor chip 40, the bonding wires 50, and/or the fine circuit traces 12 of the PCB itself can be irreparably burnt open. Therefore, the accumulation of an electrostatic charge on the components of a BGA package during package molding presents a potentially serious problem that must be overcome if BGA packages are to remain a viable semiconductor packaging candidate, especially in view of the recent trend toward chips that are smaller, higher capacity, and more highly integrated.